In many modern memory arrangements for computer systems and other electronic data processing systems the memory arrangement is not controlled as in typical traditional memory arrangements via parallel application of data, address and control signals, but via data packets which are transmitted at high speed and high frequency according to a predefined protocol between, for instance, a computer system and an interface of the memory arrangement. These data packets can contain write data, read data, addressing data, and command data.
Data packets which are sent, for instance, from a computer system to the memory arrangement can be structured in such a way that a data packet consists of a specified number of bits, which are transmitted via multiple parallel lines. The number of parallel lines can be less than the number of bits of a data packet. This is possible in that multiple successive bit groups are transmitted via parallel lines and then combined into a data packet. Thus, for example, data packets with a length of 54 bits can be transmitted via six lines, in nine successive six-bit groups.